Design of an Integrated Focal Plane Architecture for Efficient Image Processing

Monolithic integration of photodetectors, analogto-digital converters, digital processing, and data storage can improve the performance, efficiency, and cost of next-generation portable image products. These components can combine into a single processing element that can be tiled to form a pixel-level focal plane processor array. This paper describes a method to design an efficient focal plane architecture combining the topdown approach from the application suite with the bottom-up approach of fabrication technology. The focal plane architecture design provides an estimated average sustained throughput of 379 Gops/s using an area of 1588 mm in 120nm CMOS technology. The area efficiency (sustained throughput per unit of silicon area) of this focal plane architecture is 48 times that of a general purpose DSP processor. The gain in efficiency is for common image enhancement and image analysis tasks that can represent a significant portion of the total operations within an image processing sequence. Although the projected chip performance and area exceed typical system requirements, the performance and efficiency suggest enormous potential for a monolithically integrated system. Increasing the number of pixels associated with each processing element allows proportional reductions in chip performance and area.